The present invention relates in general to semiconductor memory technology, and more particularly to semiconductor memory having a flexible dual-bank architecture capable of performing two simultaneous memory operations with improved row decoding scheme.
Electronic systems often include a processor and memory. The memory in these electronic systems stores program instructions for the processor (i.e. code) and data. In many systems the code and/or data must be retained when power to the system is withdrawn. A type of memory that is capable of retaining the information stored therein even when the power is removed is known as semiconductor non-volatile memory. Some electronic devices which use non-volatile memory include personal computers, personal digital assistants, cellular telephones, digital cameras. For examples, a cellular telephone uses non-volatile memory to store telephone numbers and a personal computer uses non-volatile memory to store the computer's BIOS (basic input/output system).
There are a variety of semiconductor non-volatile memory types. One commonly used type is flash memory. Flash memories have a memory array of flash cells arranged in rows (wordlines) and columns (bitlines). A limitation of conventional flash memories relates to the differences in time it takes to perform a read operation compared to the time it takes to perform either a program operation or an erase operation. Program and erase cycles for typical flash memory devices are typically much longer than read access times. This disparity limits the speed of operation of systems in which such a memory is used.
To overcome this problem, a modified flash memory device, known as a simultaneous operation flash memory device, has been developed. In a typical simultaneous operation flash memory device, the flash memory array is partitioned into an upper memory bank and a lower memory bank. The upper and lower memory banks are normally used for different purposes. For example, the upper memory bank may be used for code storage, whereas the lower memory bank may be used for data storage. Although the simultaneous operation flash memory device is an improvement, it has a limitation of its own in that the partitioning of the upper and lower banks is fixed in the design. Such memory devices are, therefore, limited to applications that are compatible with the fixed memory partition.
To overcome the rigidity of the fixed memory partition scheme, a flexible bank partition technique has been used. In this technique, bit lines of the memory array are flexibly partitioned to form upper and lower memory banks. Because the bit lines of the memory array are split to make the partition, however, an additional column decoder (i.e. y-decoder) is required to implement the design. This not only renders the design and layout more complex, it also limits the area available for forming the memory array portion of the memory device.
Many applications for such simultaneous operation memory require a large amount of memory manufactured in a cost-effective manner. To manufacture such large memory cost effectively, the silicon area consumed by the memory needs to be minimized. Memory cell size is continuously being reduced to achieve such silicon area reduction. If the continued efforts in reducing the cell size are not accompanied by similar efforts in reducing the size of the periphery circuits which interface with the memory array, the silicon area consumed by the periphery circuit becomes the bottleneck in achieving smaller silicon area.
Row decoder is one of the circuit blocks which interfaces with the memory array. Conventionally, the wordline (row) path of a memory includes address buffers driving row predecoder which in turn drive the row decoder. The address buffer and row predecoder are generally located in the periphery area of a memory and do not physically interface with the memory array. However, the row decoder conventionally extends along one side or through the center of the memory array. With a reduction in the cell size, the memory cell pitch within which the row decoder needs to be formed (laid out) is equally reduced. Thus, to achieve an effective overall area reduction, the row decoder needs to be reduced in size.
Conventional row decoders include multi-decoding stages. In, for example, a three-stage row decoding scheme, a first decoding stage receives a first group of predecoded row address signals and in response selects a group of the decode logic in the second decoding stage. The second decoding stage, in addition to the signal(s) from the first decoding stage, receives a second set of predecoded row address signals and in response selects one of a group of wordline drivers which form the third decoding stage. The third decoding stage, in addition to the signal(s) from the second decoding stage, may receive a third set of predecoded row address signals and in response selects a wordline in one or more memory arrays.
Many row decoding schemes for minimizing the size of the row decoder, for example by reducing the number of transistors in one or more of the three decoding stages of the row decoder, have been proposed and used. Although such reduction in the number of transistors results in a smaller row decoder, no technique has been proposed which yields a substantial reduction in the silicon area consumed by the row decoder.
Thus, there is a need for a new flexible memory architecture capable of simultaneous operations and which includes a row decoding scheme resulting in a significant reduction in the silicon area consumed by the row decoder.